Heretofore, in this field, it has been desirable to provide an input buffer for a digital signal that will provide both true and complement outputs of the input signal to an address decoder. It is also desirable that during the switching of the outputs from one logic state to the other, that both outputs are not momentarily in a high logic state. This condition could cause the address decoder output to select two different addresses at the same time.
A method for preventing both complementary outputs from momentarily being in a high logic state is to design the buffer to have improved AC margin. AC margin is defined as the time delay between a first output changing states and a second (complementary) output changing states. The delay is measured from the 1/2 V.sub.cc point on each output line. With improved AC margin, the complementary buffer outputs will switch logic states at different speeds depending on the starting logic state. For example, the transition from logic high to logic low should be much faster than the transition from logic low to logic high. In this way, the high output is always lowered before the low output can switch to logic high, thereby avoiding the state in which both outputs are at logic high.
Another desirable feature of a logic buffer is hysteresis, defined as the difference in input voltage level limits which are recognized by the device as either a logic high or a logic low. For example, a device that is activated by a logic high at 3.0 V and a logic low at 1.0 V is said to have 2.0 V total hysteresis, or a 1.0 V hysteresis window around 2.0 V. The device will not respond to an input signal that falls between 1.0 V and 3.0 V. Hysteresis is a desirable feature for an input buffer due to the fact that the address input line will have a small amplitude, high frequency noise superimposed on it when it is allowed to float in a tri-state condition (the outputs of microprocessors, which generally provide the address inputs, are usually tri-stated between active cycles). This noise has many sources, including imperfect power supplies which are not completely stable or which are prone to switching noise, and the reactive components of the transmission line impedance. This superimposed noise causes uncertainty in the logic voltage levels which could cause the buffer to misinterpret the logic value of an input signal if the logic levels were defined only as being above or below a single threshold. For example, if the logic threshold is 1.5 V, a logic high signal of 1.6 V could be erroneously read as logic low if there is a 0.2 V noise fluctuation superimposed upon it.
A prior art CMOS hysteresis buffer, which could be used as the input to an address decoder input buffer, is shown in FIG. 1. It will provide a hysteresis window around 2.5 V for a CMOS or BiCMOS circuit, but it cannot be used as a TTL compatible input buffer, since a TTL compatible circuit would require a hysteresis window around 1.5 V.
Accordingly, it is desirable to provide a TTL compatible input buffer with hysteresis and improvable AC margin. It is also desirable to accomplish this with as few stages as possible to minimize the circuit's effect on the propagation speed of the input signal.